A high-speed low-complexity two-parallel radix-2<sup>4</sup> FFT/IFFT processor for UWB applications


This paper presents a high-speed, low-complexity two data-path 128-point radix-2<sup>4</sup> FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed FFT processor uses a method for compensating the truncation error of fixed-with Booth multipliers with Dadda reduction network, which keep the input and output the 8-bit width. This method leads to reduction of truncation errors compared with direct-truncated multipliers. It provides lower hardware complexity and high throughput with almost same SQNR compared with direct-truncated Booth multipliers. The proposed FFT/IFFT processor has been designed and implemented with 0.18-mum CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity.


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