A 40-MHz Bandwidth 0–2 MASH VCO-Based Delta-Sigma ADC With 35-fJ/Step FoM

Abstract

This brief presents a nonlinearity-cancelation technique in a 0-2 MASH voltage-controlled oscillator (VCO)-based delta-sigma (ΔΣ) analog-to-digital converter (ADC), where the VCO's distortion is substantially mitigated in a power-efficient way. A dual-input VCO-based quantizer topology is also proposed to implement a low-power multiple-input adder and integrator, with nox penalty in terms of nonlinearity. Fabricated in a 40-nm complementary metal-oxide-semiconductor process, a proof-of- concept 0-2 MASH 12-bit ADC prototype achieves a 66.8-dB signal-to-noise and distortion ratio with a 40-MHz bandwidth (BW) and consumes only 4.98 mW. This result extends the figure of merit of the state-of-the-art high-BW (ΔΣ) ADCs to 35 fJ/step.

Topics

12 Figures and Tables

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